Semiconductor package free of substrate and fabrication method thereof

ABSTRACT

A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part of application Ser. No.10/420,427 filed on Apr. 22, 2003, now U.S. Pat. No. 6,884,652 thedisclosure of which is expressly incorporated herein by reference.

FIELD OF INVENTION

The present invention relates to semiconductor packages and fabricationmethods thereof, and more particularly, to a semiconductor package withimproved trace routability without having to use a substrate, and amethod for fabricating the semiconductor package.

BACKGROUND OF THE INVENTION

A conventional lead-frame-based semiconductor package, such as QFN (quadflat non-leaded) package, incorporates a semiconductor chip on a leadframe serving as a chip carrier, and exposes leads of the lead frame tooutside of an encapsulant that encapsulates the chip, allowing theexposed leads as input/output (I/O) connections to be electricallyconnected to an external device such as printed circuit board (PCB).

This QFN semiconductor package is disclosed in U.S. Pat. Nos. 6,130,115,6,143,981 and 6,229,200; as shown in FIG. 6, at least one chip 20 ismounted via an adhesive (not shown) on a die pad 210 of a lead frame 21and electrically connected to a plurality of leads 211 surrounding thedie pad 210 by bonding wires 22. An encapsulant 23 formed of a resinmaterial (such as epoxy resin) encapsulates the chip 20, bonding wires22, and lead frame 21, with at least one surface 212 of each lead 211being exposed to outside of the encapsulant 23.

As shown in FIG. 7A, since the leads 211 of the lead frame 21 issubstantially proportional in number to bond pads 201 formed on anactive surface 200 of the chip 20, each bond pad 201 is electricallyconnected via a bonding wire 22 to a corresponding lead 211. The leads211 are spaced apart from the die pad 210 by a predetermined distance,such that the bonding wires 22 need to be greater in length than thedistance between the leads 211 and die pad 210 so as to effectsuccessful electrical connection between the chip 20 and leads 211. Asshown in FIG. 7B, in the case of using a highly integrated chip 20′having more bond pads 201 or higher density of bond pads 201, more leads211 are accordingly required for electrical connection with the bondpads 201, thus making the distance between the leads 211 and die pad 210and the length of bonding wires 22′ increased. Long bonding wires 22′,however, make a wire bonding process harder to implement and are easilysubject to wire sweep or shift due to resin flow impact in a moldingprocess for forming the encapsulant 23. The swept or shifted bondingwires may accidentally come into contact with each other and cause shortcircuits, which would undesirably degrade quality of electricalconnection. Further, if the leads and die pad are spaced apart from eachother too far, the wire bonding process may even be impossibly performedand thus fails to use bonding wires to electrically connect the chip tothe leads of the lead frame.

In order to reduce the length of bonding wires or the distance betweenthe leads and die pad, as shown in FIG. 8, another semiconductor packageis produced in which each lead 211 is half-etched to form a protrudingportion 213 extending toward the die pad 210 so as to reduce thedistance between the leads 211 and die pad 210, such that bonding wires22 with proper length can be used to electrical connect the highlyintegrated chip 20′ to the protruding portions 213 of the leads 211.

However, fabrication of the protruding portions 213 would undesirablyincrease costs and process complexity for making the lead frame 21′.And, during the wire bonding process, the protruding portions 213 of theleads 211 may easily dislocate in position, making it hard to preciselybond the bonding wires 22 thereto.

U.S. Pat. Nos. 5,830,800 and 6,072,239 provide a semiconductor packagefree of using a substrate, whose fabrication processes are primarilyillustrated with reference to FIGS. 9A to 9D. Referring to FIG. 9A, thefirst step is to prepare a copper-made carrier 30 and mount a mask 31over a surface of the carrier 30, wherein the mask 31 is formed with aplurality of openings 310 via which predetermined portions of thecarrier 30 are exposed. Referring to FIG. 9B, the next step is toelectrically plate a contact (or terminal) 32 in each of the openings310 and then to remove the mask 31 from the carrier 30 to expose thecarrier 30 and contacts 32. Referring to FIG. 9C, a die bonding processand a wire bonding process are in turn performed by which a chip 33 ismounted on the carrier 30 and electrically connected to the contacts 32by a plurality of bonding wires 34. Then, a molding process is carriedout to form an encapsulant 35 on the carrier 30 for encapsulating thechip 33 and bonding wires 34. Referring to FIG. 9D, the carrier 30 isetched away to expose surfaces 320, originally in contact with thecarrier 30, of the contacts 32, and the exposed contacts 32 serve asinput/output (I/O) connections of the semiconductor package to beelectrically connected to an external device (not shown).

The above semiconductor package yields a significant benefit as nothaving to use a substrate or lead frame for accommodating chips; as aresult, the encapsulant 35 is not attached to the above-mentioned leadframe 21 and there is no concern of delamination between the encapsulant35 and lead frame 21. However, similarly to the previously discussedpackaging technology, in the case of using a highly integrated chip 33with more bond pads or higher density of bond pads, more contacts 32 areaccordingly required and undesirably increase the distance between thecontacts 32 and chip 33, thereby causing the similar problems as shownin FIG. 7B that long bonding wires are subject to wire sweep or shiftand degrade quality of electrical connection.

Therefore, the problem to be solved herein is to provide a semiconductorpackage which can flexibly arrange conductive traces and effectivelyshorten bonding wires so as to improve trace routability and quality ofelectrical connection for the semiconductor package.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide a semiconductorpackage and a fabrication method thereof, which can flexibly arrangeconductive traces and effectively shorten bonding wires, therebyimproving trace routability and quality of electrical connection for thesemiconductor package.

Another objective of the invention is to provide a semiconductor packageand a fabrication method thereof without having to use a substrate tothereby reduce fabrication costs of the semiconductor package.

In accordance with the foregoing and other objectives, the presentinvention proposes a semiconductor package, comprising: a dielectricmaterial layer formed with a plurality of openings penetrating throughthe dielectric material layer; a solder material applied in each of theopenings; a first copper layer formed over the dielectric material layerand solder materials in the openings; a second copper layer formed overthe first copper layer, allowing the first and second copper layers tobe patterned to form a plurality of conductive traces, each of theconductive traces having a terminal, wherein the first copper layer issmaller in thickness than the second copper layer; a metal layer appliedon each of the terminals; at least one chip mounted on a predeterminedportion of the conductive traces; a plurality of conductive elements,such as bonding wires or solder bumps, for electrically connecting thechip to the terminals; and an encapsulant for encapsulating the chip,conductive elements, and conductive traces, with the dielectric materiallayer and solder materials being exposed to outside of the encapsulant.

A method for fabricating the above semiconductor package includes thesteps of: preparing a metal carrier; applying a dielectric materiallayer over a surface of the metal carrier, and forming a plurality ofopenings penetrating through the dielectric material layer; electricallyplating a solder material in each of the openings; electrolessly platingor sputtering a first copper layer over the dielectric material layerand solder materials in the openings; electrically plating a secondcopper layer over the first copper layer, and patterning the first andsecond copper layers to form a plurality of conductive traces, each ofthe conductive traces having a terminal, wherein the first copper layeris smaller in thickness than the second copper layer; electricallyplating a metal layer on each of the terminals; mounting at least onechip on a predetermined portion of the conductive traces; forming aplurality of conductive elements, such as bonding wires or solder bumps,to electrically connect the chip to the terminals; forming anencapsulant to encapsulate the chip, conductive elements, and conductivetraces; and etching away the metal carrier to expose the dielectricmaterial layer and solder materials.

In another embodiment, the present invention proposes a semiconductorpackage for multimedia card, comprising: a dielectric material layerformed with a plurality of openings penetrating the same, wherein theopenings are arranged along one side of the dielectric material layer; aconductive material applied in the openings of the dielectric materiallayer; a conductive layer formed on the dielectric material layer andthe conductive material, wherein the conductive layer comprises aplurality of conductive traces, and each of the conductive traces has aterminal; at least one chip mounted on the dielectric material layer andelectrically connected to the terminals of the conductive traces; anencapsulant for encapsulating the chip and the conductive layer, withthe dielectric material layer and the conductive material being partlyexposed from the encapsulant; and an insulating cover for covering theencapsulant, exclusive of the exposed part of the dielectric materiallayer and the exposed part of the conductive material.

The method for fabricating the semiconductor package for multimedia cardcomprises the steps of: preparing a metal carrier; applying a dielectricmaterial layer over a surface of the metal carrier, and forming aplurality of openings through the dielectric material layer, wherein theopenings are arranged along one side of the dielectric material layer;applying a conductive material in the openings of the dielectricmaterial layer; forming a conductive layer on the dielectric materiallayer and the conductive material, wherein the conductive layercomprises a plurality of conductive traces, and each of the conductivetraces has a terminal; mounting at least one chip on the dielectricmaterial layer, and electrically connecting the chip to the terminals ofthe conductive traces; forming an encapsulant for encapsulating the chipand the conductive layer; and mounting an insulating cover for coveringthe encapsulant, and removing the metal carrier to partly expose thedielectric material layer and the conductive material.

The conductive layer comprises a first copper layer formed on thedielectric material layer and the conductive material, and a secondcopper layer formed on the first copper layer and comprising theplurality of conductive traces. The first copper layer is smaller inthickness than the second copper layer.

The semiconductor package in the present invention yields a significantbenefit as not having to use a substrate or lead frame as a chipcarrier; instead, a chip is mounted on conductive traces which can beflexibly arranged according to bond pad distribution of the chip. Theflexible arrangement of conductive traces can effectively shorten thebonding wires used for electrically connecting the chip to terminals(bond fingers) of the conductive traces, thereby reducing an electricalconnection path between the chip and conductive traces. As a result, theprior-art problems such as short circuits caused by long bonding wiresand difficulty in performing the wire bonding process can be eliminated.Moreover, fabrication costs for the semiconductor package are alsodesirably reduced without having to use a substrate or lead frame.

BRIEF DESCRIPTION OF THE DRAWING

The present invention can be more fully understood by reading thefollowing detailed description of the preferred embodiments, withreference made to the accompanying drawings, wherein:

FIG. 1 is a cross-sectional view of a semiconductor package according toa first preferred embodiment of the invention;

FIG. 2 is a bottom view of the semiconductor package shown in FIG. 1;

FIGS. 3A-3G are schematic diagrams showing procedural steps forfabricating the semiconductor package shown in FIG. 1;

FIG. 4 is a cross-sectional view of a semiconductor package according toa second preferred embodiment of the invention;

FIG. 5 is a cross-sectional view of a semiconductor package according toa third preferred embodiment of the invention;

FIG. 6 (PRIOR ART) is a cross-sectional view of a conventionalsemiconductor package;

FIGS. 7A and 7B (PRIOR ART) are top views of the semiconductor packageshown in FIG. 6;

FIG. 8 (PRIOR ART) is a cross-sectional view of another conventionalsemiconductor package;

FIGS. 9A-9D (PRIOR ART) are schematic diagrams showing procedural stepsfor fabricating a further conventional semiconductor package;

FIG. 10 is a cross-section view of a semiconductor package according toa fourth preferred embodiment of the invention;

FIG. 11 is a bottom view of the semiconductor package shown in FIG. 10;and

FIGS. 12A-12D are schematic diagrams showing procedural steps forfabricating the semiconductor package shown in FIGS. 10 and 11.

DETAILED DESCRIPTION OF THE INVENTION

Preferred embodiments of a semiconductor package and a fabricationmethod thereof proposed by the present invention are described in detailas follows with reference to FIGS. 1 to 5.

FIRST PREFERRED EMBODIMENT

The present invention provides a semiconductor package free of using asubstrate; as shown in FIGS. 1 and 2, this semiconductor packageincludes a dielectric material layer 10 formed with a plurality ofopenings 100 penetrating through the dielectric material layer 10; asolder material 11 applied in each of the openings 100; a first copperlayer 12 formed over the dielectric material layer 10 and soldermaterials 11 in the openings 100; a second copper layer 13 formed overthe first copper layer 12, allowing the first and second copper layers12, 13 to be patterned to form a plurality of conductive traces 130 eachhaving a terminal 131, wherein the first copper layer 12 is smaller inthickness than the second copper layer 13; a metal layer 141 applied oneach of the terminals 131; at least one chip 15 mounted on apredetermined portion of the conductive traces 130; a plurality ofbonding wires 16 for electrically connecting the chip 15 to the metallayers 141 of the terminals 131; and an encapsulant 17 for encapsulatingthe chip 15, bonding wires 16, and conductive traces 130, with thedielectric material layer 10 and solder materials 11 being exposed tooutside of the encapsulant 17.

The above semiconductor package can be fabricated by procedural stepsshown in FIGS. 3A to 3G.

Referring to FIG. 3A, the first step is to prepare a metal carrier 18such as copper plate and apply a dielectric material layer 10 over asurface of the copper plate 18. The dielectric material layer 10 can bemade of a non-conductive material such as epoxy resin, polyimide, orPTFE (polytetrafluoroethylene). Then, a plurality of openings 100 areformed and penetrate through the dielectric material layer 10, allowingpredetermined portions of the copper plate 18 to be exposed via theopenings 100 that are subsequently used to form input/output (I/O)connections of the semiconductor package.

Referring to FIG. 3B, the next step is to deposit a solder material 11such as tin/lead (Sn/Pb) alloy by an electrical plating technique ineach of the openings 100 of the dielectric material layer 10 and overeach exposed portion of the copper plate 18, wherein a thickness of thesolder material 11 deposited in each opening 100 is preferably smallerthan a depth of the opening 100. Surfaces of the solder materials 11, incontact with the copper plate 18, are later to be exposed and serve asthe I/O connections of the semiconductor package. The electrical platingtechnique is conventional and not to be further described.

Then, referring to FIG. 3C, a first copper layer 12 is formed over thedielectric material layer 10 and solder materials 11 by an electrolessplating or sputtering technique, allowing the first copper layer 12 toentirely cover the dielectric material layer 10 and solder materials 11deposited in the openings 100. The first copper layer 12 is around 1-3μm thick. The electroless plating or sputtering technique isconventional and not to be further described.

Referring to FIG. 3D, a second copper layer 13 is formed by theelectrical plating technique over the first copper layer 12 and has athickness of around 15-20 μm larger than that of the first copper layer12. Then, the first and second copper layers 12, 13 are subject toexposing, developing, and etching processes to be patterned to form aplurality of conductive traces 130 each having a terminal 131; theterminals 131 are later to be used as bond fingers and electricallyconnected with a chip (not shown).

Optionally, as shown in FIG. 3DD, an insulating layer 140, such assolder mask or polyimide, can be applied over the conductive traces 130for protection purposes. The insulating layer 140 covers the conductivetraces 130 with the terminals 131 being exposed to outside of theinsulating layer 140, and the exposed terminals 131 subsequently serveas bond fingers.

Thereafter, a metal layer 141 is formed by the electrical platingtechnique on each terminal (or bond finger) 131 of the conductive traces130. The metal layer 141 can be a silver (Ag) layer or a nickel/gold(Ni/Au) layer, preferably having good bondability with a conductiveelement (such as bonding wire, not shown) for being electricallyconnected to a chip (not shown).

Referring to FIG. 3E, a chip 15 is prepared, having an active surface150 formed with a plurality of electronic elements and circuits (notshown) and a non-active surface 151 opposed to the active surface 150. Adie bonding process is performed to attach the non-active surface 151 ofthe chip 15 via an adhesive (not shown) to a predetermined portion ofthe conductive traces 130.

Then, a wire bonding process is performed to form and bond a pluralityof bonding wires 16 to the active surface 150 of the chip 15 and to themetal layers 141 on the bond fingers 131, whereby the chip 15 can beelectrically connected to the bond fingers 131 via the bonding wires 16.

Referring to FIG. 3F, a molding process is carried out by which thedie-bonded and wire-bonded semi-fabricated structure is placed in aconventional encapsulation mold (not shown), and a resin material suchas epoxy resin is injected and filled into a mold cavity (not shown) ofthe encapsulation mold to form an encapsulant 17 that encapsulates andprotects the chip 15, bonding wires 16, and conductive traces 130against damage from external moisture or contaminant. After the resinmaterial is cured, the encapsulation mold is removed and the encapsulant17 is completely fabricated.

Finally, referring to FIG. 3G, after forming the encapsulant 17, asingulation process is performed and uses a cutting machine 4 to cutthrough the encapsulant 17. Then the copper plate 18 is removed by anetching process from the dielectric material layer 10, and thussurfaces, originally in contact with the copper plate 18, of thedielectric material layer 10 and solder materials 11 in the openings 100are exposed outside. This thereby completes fabrication of thesemiconductor package shown in FIGS. 1 and 2, and the exposed soldermaterials 11 act as I/O connections to be electrically connected to anexternal device such as printed circuit board (PCB, not shown).

The above semiconductor package yields a significant benefit as nothaving to use a substrate or lead frame as a chip carrier; instead, achip is mounted on conductive traces which can be flexibly arrangedaccording to bond pad distribution of the chip. The flexible arrangementof conductive traces can effectively shorten the bonding wires used forelectrically connecting the chip to terminals (bond fingers) of theconductive traces, thereby reducing an electrical connection pathbetween the chip and conductive traces. As a result, the prior-artproblems such as short circuits caused by long bonding wires anddifficulty in performing the wire bonding process can be eliminated.Moreover, fabrication costs for the semiconductor package are alsodesirably reduced without having to use a substrate or lead frame.

SECOND PREFERRED EMBODIMENT

FIG. 4 illustrates a semiconductor package according to a secondpreferred embodiment of the invention. As shown in the drawing, thissemiconductor package differs from that of the above first embodiment inthat the chip 15 is mounted in a flip-chip manner on the conductivetraces 130. In particular, during a die bonding process, the activesurface 150 of the chip 15 is directed toward the conductive traces 130and electrically connected via solder bumps 16′ to the terminals 131 ofthe conductive traces 130 where the terminals 131 serve as bond padsused to be bonded with the solder bumps 16′. Alternatively, aninsulating layer 140 can be applied over the conductive traces 130 withthe terminals 131 being exposed and connected to the solder bumps 16′.

Compared to the use of bonding wires for electrically connecting thechip and conductive traces, the flip-chip technology can further reducean electrical connection distance from the chip 15 to conductive traces130 via solder bumps 16′, thereby assuring quality of electricalconnection between the chip 15 and conductive traces 130.

Moreover, the non-active surface 151 of the chip 15 is optionallyexposed to outside of the encapsulant 17 encapsulating the chip 15. Thisallows heat produced from operation of the chip 15 to be effectivelydissipated via the exposed non-active surface 151, thereby improvingheat dissipating efficiency of the semiconductor package.

THIRD PREFERRED EMBODIMENT

FIG. 5 illustrates a semiconductor package according to a thirdpreferred embodiment of the invention. This semiconductor packagediffers from that of the above first embodiment in that a plurality ofsolder balls 19 are implanted on the exposed solder materials 11 to forma ball grid array. These solder balls 19 serve as I/O connections of thesemiconductor package to be electrically connected with an externaldevice (not shown).

FOURTH PREFERRED EMBODIMENT

FIGS. 10 and 11 show a semiconductor package for use in a multimediacard according to a fourth preferred embodiment of the invention. Thefourth embodiment is similar to the above first embodiment, withdifferences in that the openings 100 of the dielectric material layer 10are arranged along one side of the dielectric material layer 10, aninsulating cover 5 is additionally provided to cover the encapsulant 17but not covering the exposed parts of the dielectric material layer 10and the solder material 11, and the chip 15 is mounted on the dielectricmaterial layer 10.

As shown in FIGS. 10 and 11, the semiconductor package for multimediacard according to the fourth embodiment of the invention comprises adielectric material layer 10 formed with a plurality of openings 100penetrating the same, wherein the openings 100 are arranged along oneside of the dielectric material layer 10; a conductive material 11applied in the openings 100 of the dielectric material layer 10; aconductive layer 1 formed on the dielectric material layer 10 and theconductive material 11, wherein the conductive layer 1 comprises aplurality of conductive traces 130, and each of the conductive traces130 has a terminal 131; at least one chip 15 mounted on the dielectricmaterial layer 10 and electrically connected to the terminals 131 of theconductive traces 130; an encapsulant 17 for encapsulating the chip 15and the conductive layer 1, with the dielectric material layer 10 andthe conductive material 111 being partly exposed from the encapsulant17; and an insulating cover 5 for covering the encapsulant 17, exclusiveof the exposed part of the dielectric material layer 10 and the exposedpart of the conductive material 11.

In the fabrication method of the semiconductor package shown in FIGS. 10and 11, after the processes shown in FIGS. 3A and 3B that a metalcarrier 18 is prepared and applied with a dielectric material layer 10thereon having a plurality of openings 100, and a conductive materialsuch as a solder material 11 is deposited in the openings 100 of thedielectric material layer 10, referring to FIG. 12A, a conductive layer1 is formed on the dielectric material layer 10 and the solder material11, wherein the conductive layer 1 comprises a first copper layer 12 anda second copper layer 13. Preferably, the first copper layer 12 isfirstly formed over the dielectric material layer 10 and the soldermaterial 11 by for example the conventional electroless plating orsputtering technique. The first copper layer 12 is approximately 1 to 3μm thick. Then, the second copper layer 13 is formed over the firstcopper layer 12 by for example the conventional electroplatingtechnique. The second copper layer 13 has a thickness of approximately15 to 20 μm, which is larger than the thickness of the first copperlayer 12. Subsequently, the first and second copper layers 12, 13 arepatterned by for example exposing, developing and etching processes toform a plurality of conductive traces 130 each having a terminal 131.

Optionally, as shown in FIG. 12AA, an insulating layer 140 can beapplied over the conductive traces 130 for the protection purpose. Theinsulating layer 140 can be made of solder mask or polyimide. Theinsulating layer 140 covers the conductive traces 130, with theterminals 131 of the conductive traces 130 being exposed from theinsulating layer 140.

Then, a metal layer 141 can be formed on the terminals 131 of theconductive traces 130 by for example the conventional electroplatingtechnique. The metal layer 141 can be made of silver or a nickel/goldalloy, which preferably has good bondability with subsequent conductiveelements such as bonding wires or solder bumps to be bonded thereto.

Referring to FIG. 12B, at least one chip 15 is mounted on the dielectricmaterial layer 10, and is electrically connected to the terminals 131 ofthe conductive traces 130 by a plurality of bonding wires 16. Thebonding wires 16 are bonded to the chip 15 and to the metal layer 141 onthe terminals 131 of the conductive traces 130. Alternatively, the chipcan be electrically connected to the terminals of the conductive tracesby a plurality of solder bumps, similarly to the structure of the secondembodiment shown in FIG. 4.

Referring to FIG. 12C, a molding process is performed to form anencapsulant 17 for encapsulating the chip 15, the bonding wires 16 andthe conductive layer 1.

Finally, referring to FIG. 12D, a singulation process is performed tocut through the encapsulant 17, such that an insulating cover 5 isprovided to cover the encapsulant 17 and the metal carrier 18 is removedfrom the dielectric material layer 10 by for example an etching process,making the dielectric material layer 10 and the solder material 11partly exposed. The exposed part of the solder material 11 comprises aplurality of exposed contacts arranged along the side of the dielectricmaterial layer 10 to serve as I/O connections for establishing externalelectrical connection for the semiconductor package.

The invention has been described using exemplary preferred embodiments.However, it is to be understood that the scope of the invention is notlimited to the disclosed embodiments. On the contrary, it is intended tocover various modifications and similar arrangements. The scope of theclaims, therefore, should accord with the broadest interpretation so asto encompass all such modifications and similar arrangements.

1. A semiconductor package for multimedia card, comprising: a dielectricmaterial layer formed with a plurality of openings penetrating the same,wherein the openings are arranged along one side of the dielectricmaterial layer; a conductive material applied in the openings of thedielectric material layer; a conductive layer formed on the dielectricmaterial layer and the conductive material, wherein the conductive layercomprises a plurality of conductive traces, and each of the conductivetraces has a terminal; at least one chip mounted on the dielectricmaterial layer and electrically connected to the terminals of theconductive traces by a plurality of bonding wires or solder bumps; anencapsulant for encapsulating the chip and the conductive layer, withthe dielectric material layer and the conductive material being partlyexposed from the encapsulant; and an insulating cover for covering theencapsulant, exclusive of the exposed part of the dielectric materiallayer and the exposed part of the conductive material.
 2. Thesemiconductor package of claim 1, further comprising a metal layerapplied on the terminals of the conductive traces.
 3. The semiconductorpackage of claim 2, wherein the metal layer is made of silver or anickel/gold alloy.
 4. The semiconductor package of claim 1, furthercomprising an insulating layer applied on the conductive traces, withthe terminals of the conductive traces being exposed from the insulatinglayer.
 5. The semiconductor package of claim 4, wherein the insulatinglayer is made of solder mask or polyimide.
 6. The semiconductor packageof claim 1, wherein the conductive material comprises a solder material.7. The semiconductor package of claim 6, wherein the solder materialcomprises a tin/lead alloy.
 8. The semiconductor package of claim 1,wherein the conductive layer comprises a first copper layer formed onthe dielectric material layer and the conductive material, and a secondcopper layer formed on the first copper layer and comprising theplurality of conductive traces.
 9. The semiconductor package of claim 8,wherein the first copper layer is smaller in thickness than the secondcopper layer.
 10. The semiconductor package of claim 1, wherein thedielectric material layer is made of a material selected from the groupconsisting of epoxy resin, polyimide and polytetrafluoroethylene (PTFE).11. The semiconductor package of claim 1, wherein the exposed part ofthe conductive material comprises a plurality of exposed contactsarranged along the side of the dielectric material layer.